1. Field of the Invention
The invention relates to a method for analyzing circuit pattern, and more particularly to a method for monitoring process window of circuit patterns.
2. Description of the Prior Art
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Another important part of manufacturing yield control is determining the cause of defects on wafers such that the cause of the defects can be corrected to thereby reduce the number of defects on other wafers. Often, determining the cause of defects involves identifying the defect type and other attributes of the defects such as size, shape, composition, etc. Since inspection typically only involves detecting defects on wafers and providing limited information about the defects such as location on the wafers, number of defects on the wafers, and sometimes defect size, defect review is often used to determine more information about individual defects than that which can be determined from inspection results. For instance, a defect review tool may be used to revisit defects detected on a wafer and to examine the defects further in some manner either automatically or manually.
Defect review typically involves generating additional information about defects at a higher resolution using either a high magnification optical system or a scanning electron microscope (SEM). The higher resolution data for the defects generated by defect review is more suitable for determining attributes of the defects such as profile, roughness, more accurate size information, etc. Defect analysis may also be performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defect analysis may be performed to determine information such as composition of the defects. Attributes of the defects determined by inspection, review, analysis, or some combination thereof can be used to identify the type of the defect (i.e., defect classification) and possibly a root cause of the defects. This information can then be used to monitor and alter one or more parameters of one or more semiconductor fabrication processes to reduce or eliminate the defects.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. For example, metal line pattern deforms has been found due to residual stress in TiN metal hard mask as interconnect metal and via critical dimensions shrunk with advanced technology node. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. As such, determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process induced failures may, in some cases, tend to be systematic. That is, process induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially systematic, electrically relevant defects is important because eliminating such defects can have a significant overall impact on yield.
Accordingly, it may be advantageous to develop systems and methods for detecting design and process defects on a wafer and/or reviewing defects on a wafer such that defects from various sources can be detected, reviewed, and analyzed using a single system or method and to develop systems and methods for selecting one or more features within a design for use as process monitoring features that provide an earlier indication of a process deviation than currently used process monitoring features.